This invention relates to a bit synchronizer for digital data and, more particularly, this invention relates to a tracking bit synchronizer for use in high density digital magnetic tape recorders.
Digital data transmitted over a data channel (such as a communication channel or a record/reproduce channel) is frequently transmitted without specific data rate information. Thus, unencoded digital data has data transitions which are unrelated to the data rate. Typically, a bit synchronizer includes a phase locked loop which serves as a clock regeneration circuit. This circuit allows recovery of data from a recording or transmission where the data is available without a corresponding clock signal. The regenerated clock defines the timing of the data and is used to detect, decode and process the data.
A functional block diagram of a typical bit synchronizer is shown in FIG. 1. As shown, zero crossing detector 10 detects the zero crossings of an incoming data signal. Phase detector 12 compares the zero crossings of the incoming data signal to a clock signal produced by voltage control oscillator (VCO) 16. The result of this phase comparison is filtered by filter 14 and the filtered voltage is used to adjust VCO 16 to achieve frequency and phase lock with the incoming data signal. This clock signal is used to synchronize latch 18 and decoder 20. Such bit sychronizers require phase detectors which allow recovery of phase information from edges in the data, but, which do not give false phase information in the absence of data edges. This is needed since any consecutive 1's or consecutive 0's do not have an edge between them in data formats which are not self clocking. The phase detector of the bit synchronizer of FIG. 1 typically includes a mixer, exclusive or gates, or sequential logic circuits. A disadvantage of such phase detector circuits is that a clock edge without a corresponding data edge would cause them to indicate a phase error, which would send a false correction signal to VCO 16.
Bit synchronizer phase detectors typically include an early/late gate which only produces phase error information near a data transition (see, for example, U.S. Pat. 4,766,397, issued Aug. 23, 1988, Inventor Adams; and U.S. Pat. 4,280,224, issued Jul. 21, 1981, Inventor Chethik).
The ability of the early/late gate detector to tolerate missing data edges may also result in false bit synchronizer locks to occur at incorrect clock rates. Thus, for example, digital data encoded in a bi-phase mark encoding format produces two clocks for each data cell, such that there is a clock edge for each data edge, plus an additional edge at mid-bit time. Repeating data patterns will also be sensitive to false locks at other frequencies which are not necessarily at simple multiples of the correct data rate. Since the clock of a phase locked loop can lock to data at a number of clock rates, only one of which is correct, bit synchronizers (such as those disclosed in the latter two patents) have typically been constrained to operate in a small range (plus or minus 1 percent to plus or minus 4 percent) around the correct data rate. In operation, such bit synchronizers will be adjusted for frequency of operation at normal set up and alignment and at appropriate maintenance intervals. For many applications, the data rate is constant and this type of operation is adequate. However, such bit synchronizers are inadequate in applictions where the signal sources vary data rate by design (such as down-looking radars) or where the incoming data signal varies in frequency due to doppler or other environmental effects. Moreover, due to time and temperature drifts, even the most stable of bit synchronizers will not be at optium adjustment all the time, thus, producing inaccurate clock signals.
U.S. Patent 4,375,693, issued Mar. 1, 1983, Inventor Kuhn, and, U.S. Pat. 4,375,694, Mar. 1, 1983, Inventor Kuhn, disclose a bit synchronizer capable of operation over broad range of frequencies by means of an auto range capability which automatically steps the frequency of the voltage controlled oscillator of a phase locked loop through half octaves within an arbitrarily large range. However, the bit synchronizer disclosed in these patents has a narrow lock range (1 percent) and, thus, is not suitable for applications where the ability to lock to a wide range of data rates without readjustment is desirable.
Thus, it is desirable that a bit synchronizer have the ability to lock to a wide range of data rates without readjustment. It is also desirable that the bit synchronizer be able to follow changing data rates and to compensate automatically for any temperature drifts and aging. The bit synchronizer should be immune to false phase locks.